This invention relates to buffer circuits, and more particularly to buffer circuits comprised of field effect transistors on an integrated circuit. Basically, buffer circuits perform the task of receiving input signals that switch between two input levels, and generating output signals which switch between two different voltage levels. Typically, the two input levels are designated V.sub.IL and V.sub.IH ; while the output signals are designated V.sub.OL and V.sub.OH. In this nomenclature, V.sub.IL represents a low input voltage, V.sub.IH represents a high input voltage, V.sub.OL represents a low output voltage, and V.sub.OH represents a high output voltage.
As a specific example of the above, buffer circuits commonly are used to convert T.sup.2 L input signals to output signals that are more compatible for use with MOS circuits. For T.sup.2 L signals, V.sub.IL and V.sub.IH respectively are approximately 0.8 volts and 2.0 volts. In comparison, suitable V.sub.OL and V.sub.OH voltage levels for MOS circuits are approximately 1.0 volts and 10.0 volts.
It is desirable for the buffer circuit to have a "trip" voltage lying approximately midway between V.sub.IH and V.sub.IL. "Trip" voltage is defined as the input voltage which causes the output signal to lay midway between V.sub.OH and V.sub.OL. Thus a trip voltage midway between V.sub.IL and V.sub.IH gives the circuit maximum noise immunity. That is, spurious transitions on the input signal from V.sub.IL or V.sub.IH should not cause the output to switch; and this is achieved by setting the trip voltage midway between V.sub.IL and V.sub.IH.
Unfortunately, however, in many prior art buffer circuits, the trip voltage varies directly with the threshold voltage of the field effect transistors which comprise the buffer circuit. The threshold voltage is that voltage at which the field effect transistors begin to substantially conduct. This voltage varies greatly with process variations, VBB or body voltage variations and temperature variations.
For example, process variations such as gate oxide thickness, substrate doping concentration, implant density, and channel length variations due to lateral diffusion of implants typically cause the threshold voltage to vary between 0.5 volts and 1.5 volts at a fixed temperature and fixed body voltage. Further, VBB voltage variations in the range of .+-.20% around its nominal value typically produces threshold voltage variations of about 200 millivolts. Such a range of VBB is typically required for part qualification by various chip users. Further, threshold voltage typically decreases by approximately 300 millivolts as the temperature varies from 0.degree. C. to 100.degree. C. All of these variations in threshold voltage cause corresponding variations in trip voltage for buffer circuits, which in turn gives them lower noise immunity.
Accordingly, it is one object of the invention to provide an improved buffer circuit.
Another object of the invention is to provide a buffer circuit having a selectable trip voltage.
Still another object of the invention is to provide a buffer circuit having a trip voltage that is substantially insensitive to threshold voltage variations.